Fb-Cpu: A Minimal Rtl Processor Architecture for Enhancing Undergraduate Digital Design and Computer Architecture Education

Abstract

This study presents the design and educational deployment of FB-CPU, a minimal, fully synthesizable processor architecture developed for undergraduate digital design and computer architecture education. FB-CPU is a compact Von Neumann–style processor featuring a 10-bit instruction format, a simple 9-instruction ISA, and a four-register datapath consisting of PC, IR, ACC, and a finite-state control register, as derived from the provided teaching specification. The processor supports memory-mapped execution on a small Block RAM and operates through a clearly defined multi-cycle state machine, enabling students to observe the fetch–decode–execute cycle at an RTL granularity. The architecture was intentionally designed to minimize structural complexity while maximizing conceptual transparency, thereby enabling learners to implement the ALU, datapath, and control logic directly in Verilog. Students additionally verify their designs using a simulation environment and FPGA deployment workflow, following the project specifications documented in the course materials. The pedagogical contribution of this work lies in offering a processor that is simple enough to be built from scratch within an introductory course, yet rich enough to illustrate fundamental concepts such as instruction encoding, state-based microarchitectures, memory interfacing, and sequential logic design. Classroom deployments demonstrate that FB-CPU effectively improves student understanding of RTL modeling, control-unit design, and machine-level programming by grounding theoretical concepts in hands-on implementation. The processor and accompanying toolchain (including the Von Neumann simulator, test cases, and FPGA lab exercises) provide a reproducible and scalable framework for institutions seeking to integrate practical CPU design exercises into digital systems curricula.