An Area-Efficient QCA-Based Multiplier for High-Performance Nanoscale DSP and Embedded Computing

Abstract

Multiplication is a fundamental operation in digital signal processing, embedded computing, and nanoscale arithmetic data paths, where area, delay, and energy efficiency are critical design constraints. However, nanoscale multiplier design is challenged by high interconnect complexity, frequent wire crossings, clock-zone synchronization issues, and the rapid growth of area and latency with operand size. Quantum-dot cellular automata (QCA) technology offers a promising post-CMOS platform for compact arithmetic circuit realization through field-coupled computation and transistor-free switching. This paper presents a single-layer QCA-based Dadda Tree Multiplier (DTM) using layout-aware integration of compact half-adder, full adder, XOR, and carry-skip adder modules. The proposed design emphasizes partial-product compression, routing compactness, clock-aware organization, and area-efficient final accumulation. Functional verification is performed using QCADesigner 2.0.3, while energy-related behavior is evaluated using QCADesigner-E under the conventional QCA simulation framework. The proposed DTM consists of 4282 cells and occupies 6.14 μm2. Compared with a recent compact QCA multiplier baseline, the proposed architecture reduces cell count by 59.12% and occupies area by 39.80%, while maintaining competitive clocking latency. These results indicate that layout-aware integration of arithmetic modules can substantially improve the area efficiency of QCA-based multipliers, making the proposed design a compact arithmetic core for future nanoscale embedded and signal-processing systems.