Selvi, Osman

Profile URL
https://hdl.handle.net/20.500.14627/502
Name Variants
Job Title
Doktor Öğretim
Email Address
osman.selvi@fbu.edu.tr
Main Affiliation
Bilgisayar Mühendisliği Bölümü
Status
Website
ORCID ID
0000-0001-8666-9984
Scopus Author ID
57194594884
Turkish CoHE Profile ID
Google Scholar ID
WoS Researcher ID
Files
photo_376810.png.png (215.61 KB)

Research Topics

Domains
Physical Sciences
Fields
Environmental Science
Subfields
Water Science and TechnologyGlobal and Planetary ChangeEnvironmental Engineering
Specific Research Areas
Hydrology and Watershed Management Studies
Hydrology and Drought Analysis
Hydrological Forecasting Using AI

Sustainable Development Goals

SDG data is not available

Publication Collaboration

Affiliation Name Count
Istanbul Aydın University 1
1 / 1
Data obtained from OpenAlex
Scholarly Output

2

Articles

2

WoS Citation Count

0

Scopus Citation Count

0

Filters

20262

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Author of Publication: search.filters.isAuthorOfPublication.e7aa4a9d-e461-47e8-a3f0-6f3dcff7f79a

Scholarly Output Search Results

Now showing 1 - 2 of 2
  • Article
    Fault-Tolerant QCA-Based Parity Pre-Filtering Circuits for Lightweight Edge-IoT Transaction Screening
    (MDPI, 2026) Ahmadpour, Seyed-Sajad; Ajlouni, Naim; Zohaib, Muhammad; Selvi, Osman
    Edge Internet of Things (IoT) blockchain deployments increasingly rely on continuous transaction ingestion from resource-constrained IoT devices to nearby edge gateways over heterogeneous wireless links. In this setting, transient channel noise and packet corruption can inject invalid payloads into the edge processing pipeline and trigger unnecessary buffering, parsing, and, most critically, computationally expensive cryptographic operations such as digital signature verification. This leads to wasted computation, increased latency, and reduced energy efficiency at the edge, particularly under dense IoT traffic. This paper presents an energy-aware and fault-tolerant Quantum-Dot Cellular Automata (QCA)-based integrity pre-filter for IoT-to-edge blockchain transaction ingestion. At the circuit level, we adapt and modify a previously reported fault-tolerant five-input majority gate (MV5) structure and use it as a robust primitive for nanoscale integrity-screening circuits. Building on this modified MV5, we design a set of QCA integrity blocks, including a parity checker, a compact XNOR gate circuit, a parity-bit generation circuit, and a sender-to-channel/receiver nano-communication integrity workflow suitable for early screening of corrupted payloads. Compared with the best previously reported baseline considered in this study, the modified MV5 achieves 76.47% tolerance to single-cell omission defects, corresponding to a 17.47 percentage-point increase and an approximately 29.61% relative improvement over the prior 59% omission-tolerance result, while preserving 100% tolerance against extra-cell deposition defects. At the system level, the proposed circuit is discussed as a potential early screening stage for edge-IoT blockchain transaction ingestion. A bounded analytical model is used to estimate the possible reduction in unnecessary signature-verification workload under assumed corruption and detection conditions. This analysis is not intended as a deployment-level validation; full edge-node implementation, throughput measurement, queueing-delay evaluation, real traffic traces, retransmission behavior, and empirical signature-verification profiling remain future work. The proposed parity/chunk-parity pre-filter is designed for low-cost detection of random transmission-induced corruption and does not replace cryptographic authentication, hashing, digital signatures, CRC-based detection, or blockchain validation. All proposed designs are validated using QCADesigner tools.
  • Article
    An Area-Efficient QCA-Based Multiplier for High-Performance Nanoscale DSP and Embedded Computing
    (MDPI, 2026) Ahmadpour, Seyed‐sajad; Zohaib, Muhammad; Vahabi, Mohsen; Selvi, Osman
    Multiplication is a fundamental operation in digital signal processing, embedded computing, and nanoscale arithmetic data paths, where area, delay, and energy efficiency are critical design constraints. However, nanoscale multiplier design is challenged by high interconnect complexity, frequent wire crossings, clock-zone synchronization issues, and the rapid growth of area and latency with operand size. Quantum-dot cellular automata (QCA) technology offers a promising post-CMOS platform for compact arithmetic circuit realization through field-coupled computation and transistor-free switching. This paper presents a single-layer QCA-based Dadda Tree Multiplier (DTM) using layout-aware integration of compact half-adder, full adder, XOR, and carry-skip adder modules. The proposed design emphasizes partial-product compression, routing compactness, clock-aware organization, and area-efficient final accumulation. Functional verification is performed using QCADesigner 2.0.3, while energy-related behavior is evaluated using QCADesigner-E under the conventional QCA simulation framework. The proposed DTM consists of 4282 cells and occupies 6.14 μm2. Compared with a recent compact QCA multiplier baseline, the proposed architecture reduces cell count by 59.12% and occupies area by 39.80%, while maintaining competitive clocking latency. These results indicate that layout-aware integration of arithmetic modules can substantially improve the area efficiency of QCA-based multipliers, making the proposed design a compact arithmetic core for future nanoscale embedded and signal-processing systems.